Wanted to bring to your attention a potential error in one of your reference design modules up on the git repo.
Tool used : Vivado 2016.4
H/w: 7 series FPGA (zynq)
Git branch: master, hdl_2016_r1 and possibly all branches newer than 2014_r1
Folder: / library/ common
The module 'ad_mmcm_drp.v' seems to instantiate the the MMCM_ADV primitive expecting a defined input for the CLKINSEL pin (1 or 0 depending on CLKIN1 or CLKIN2 to be used as the input clock). > line # 181 in ad_mmcm_drp.v
However the 'ad_serdes_clk' module that instantiates the clock manager (ad_mmcm_drp) does NOT provide the CLKINSEL input causing Vivado to tie this pin to 0 during implementation. This means the mmcm is now expecting CLKIN2 to be the reference clock input. However the ad_serdes_clk module does NOT provide an input for CLKIN2 (clk_2) input either, causing this input to be tied low during implementation as well.
In Vivado 2016.4 atleast this causes an implementation and therefore bit generation error since timing constraints are NOT met.
I have the ad_mmcm_drp.v module from an older branch and in this module the CLKIN2 is set to 1'0 and CLKINSEL to 1'b1 which seems to be the correct values to pass to this module (assuming that a valid clock is present on CLKIN1).
Am I correct in thinking this is a design mistake? or am I missing something?
Was there was a reason to define a clk_sel and clk_2 for some future design?
If this is the case then clk_sel should be kept active high to ensure proper operation untill the reference design actually provides a valid input to these two pins.