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AD7266 with FPGA

Question asked by ananthan on Mar 24, 2017
Latest reply on May 3, 2017 by jcolao

Hello,I am using AD7266 (little old) to communicate FPGA. In the data sheet I found that the data is clocked out in falling edge of the sclk. I  have used the rising edge for counting 14 sclk  cycles is it correct? help me,

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