I have a prototype setup where I have an HMC7043 eval board that then feeds clock and sync signals to two other HMC7043 eval boards. So it is effectively a cascaded structure with a single HMC7043 at the root node, and then 2 HMC7043s in parallel at the next level. I am trying to synchronize the output clocks of the 2 HMC7043s that are at the second level. If I configure each of those devices to output a clock signal that is a divided version of the input clock (e.g. divide by 2, 4, or 8), I observe that their output clocks are synchronized after I request the first device to issue a sync pulse. That is, the rising edge of their output clocks align as expected. I can even set their dividers to different values from one another (e.g. set one device to divide by 2 and the other to divide by 8), and I still observe the expected behavior (their output clock rising edges align after I send the sync pulse). However, if I change one of those devices to a divide by 1, and then issue the sync pulse, the rising edges of their output clocks no longer align. I do have the device configured so that the divide by 1 clock output mux selection is set to channel divider, so it should be going through the divider just as it does in the other cases. Can you think of something I might be doing wrong here? Is there anything special I need to do differently for the divide by 1 case?