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How to achieve the high SFDR performance specified by the datasheet

Question asked by hoo on Mar 23, 2017
Latest reply on Apr 12, 2017 by DougI

I recently designed a data acquisition board with AD9684,it is a simple FMC mezzanine card,I run the card on Xilinx KC705。here is the test result(with LC bandpass filter and 16384 points FFTs):

(In the figure above,single sideband power is -11.6dB which equal to -8.6dBFS input power, Spur is HD2 71.83dBc below input bar,so SFDR is -80.43dBFS ,the Typ is -83dBFS in datasheet.   )

 

the sample clock of AD9684 is driven by HMC7044 with 20MHz XO reference and only PLL2 is used,I use a much lower input power (-8.6dBFS) than testing condition(-1dBFS) in datasheet,the SFDR performance is still far from datasheet.

 

How can i get the perfect SFDR testing data?

Must i use a high performance crystal oscillator instead of PLL(HMC7044) as AN-835 recommended?

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