I would like to read an audio file (from external memory), resample and stream it out as TDM
any help or exmaple code is more than welcome
Please let me know on which processor you are referring to.
sorry forgot to mention it
it is for sharc ADSP-21469
I think that you should have the audio file in .dat format and place directly on the external DDR2. One of the SPORT can be used for taking the data from DDR2 and send this to the SRC in TDM mode as per the sample rate of the audio file. The TDM output of the SRC can be received by another SPORT and placed on either internal memory/external memory.
I have added the example codes for SPORT DMA from/to DDR2 memory and SRCs in TDM mode. You may use them as reference and start your application code development. If you need any other information, please provide exact details about the application.
this is in asm do you have an example code in c as well??
I do not have the C codes for ADSP-21469 processors. But I have the SRC TDM mode example code in C for ADSP-21369 processors. You can use the same code with the ADSP-21469 processors with some modifications. This code also shows how the SPORTs can be used in DMA chaining mode.
what kind of modifications?
You may have to change the project for ADSP-21469 processors and generate a new LDF file. The internal memory map is different for both the processors. Change the header file reference to ADSP-21469 and remove the DAI_PIN_PULLUP registers from the code. This should help you run the same code on ADSP-21469 processors.
what if i receive the audio thru spdif port?
how can I convert the sample rate then?
Yes. You can connect the SPDIF receiver output directly to the SRC Input. You can connect the DIR_CLK and DIR_FS signals to the SRC CLK and FS inputs. For the output portion you can connect another SPORT/PCG to generate clock and frame sync. You may have something like this:
SRU (DIR_CLK_O, SRC0_CLK_IP_I); SRU (SPORT1_CLK_O, SRC0_CLK_OP_I);
SRU (DIR_FS_O, SRC0_FS_IP_I);SRU (SPORT1_FS_O, SRC0_FS_OP_I);
SRU (DIR_DAT_O, SRC0_DAT_IP_I); SRU (SRC0_DAT_OP_O, SPORT1_DA_I);
I've taken a look at the SRC TDM example, and have a few questions:
1. why is MPHASE being set for all SRCs? Since SRC0 is the first and is chained through the rest, I assume it is the master and MPHASE should be cleared.
2. the SPORT setup noted that the SPORT setup for SPMCTL uses a setting of 2 for the Multichannel Frame Delay. Is this the standard TDM setup supported for the ASRCs in TDM mode? Trying to get an answer for http://ez.analog.com/message/118056#118056
Sorry for the delay in getting back on this. The MPHASE bit is used for using the SRC in matched phase mode. This is applicable only for the processors which support 140 dB SRCs(ADSP-21488). For other processors this bit will not be used. Please refer the matched-phase mode chapter in the ADSP-214XX HRM for more details.
The multichannel Frame Delay needs to be chosen based on the application requirements. The SRC doesn't expect any specific value for this. Since multiple SRCs are connected in the chained manner the frame delay needs to be added to make sure that the data is transmitter/received correctly. Please refer to the multichannel frame delay on the ADSP-214XX HRM for more details.
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