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HIGH SPEED ADC (AD9239)sync problem

Question asked by wushuang on Mar 23, 2017
Latest reply on Apr 4, 2017 by David.Buchanan

Hi!

   my design used AD9239-210,input 200MHz clock,2 chip on the PCB,8 channels  from the same clock sources.
after AD9239,data into  FPGA through GTX.

 

      (introduction in datasheet)
      To minimize skew and time misalignment between eachchannel of the digital outputs, the following actions should be taken to ensure that each channel data packet is within ±1 clockcycle of its specified switching time. For some receiver logic,this is not required.
1. Full power-down through external PDWN pin.
2. Chip reset via external RESET pin.
3. Power back up by releasing external PDWN pin


  after configure the two chip ,i get the data "CCAA DDBB 3553 66A5"by COMMA ALIGN function using in GTX,

however,there is difference betwwen channels.for example:

CH1: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

CH2: DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA

CH3: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

CH4: 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 

CH5: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

CH6: DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA

CH7: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

CH8: 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 

NOT that:

CH1: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

CH2: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

CH3: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

CH4: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 

CH5: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

CH6: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

CH7: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

CH8: CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5 CCAA DDBB 3553 66A5

How can i deal with it to get sync for 8 channels????

Assuming that the eight channels are aligned and sync under the training pattern, follow the steps below :

(introduction in datasheet)
1. Initialize a soft reset via Bit 5 of Register 0 (see Table 15).
2. All PGMx pins are automatically initialized as sync pins by default. These pins can be used to lock the FPGA timingand data capture during initial startup. These pins arerespective to each channel (PGM3 = Channel A).
3. Each sync pin is held low until its respective PGMx pinreceives a high signal input from the receiver, during which
time the ADC outputs a training pattern.
4. The training pattern defaults to the values implemented by the user in Register 19 through Register 20.
5. When the receiver finds the frame boundary, the sync identification is deasserted high via the sync pin or via a SPI write. The ADC outputs the valid data on the next packet boundary. The time necessary for sync establishment is highly dependent on the receiver logic processing. Refer to theSwitching Specifications section; the switching timing is directly related to the ADC channel.

 

Each channel PGM pin is enabled for the moment, the ADC output after 66A5, if the sampling data is delayed, the delay is about how much and output what character data????

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