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FMCOMMS2 - hdl_2016_r2 - timing error from Vivado GUI

Question asked by jferment on Mar 22, 2017
Latest reply on Apr 12, 2017 by oppradhan

I recently pulled down the hdl_2016_r2 branch and I have no problems building the design from CYGWIN using the provided Makefile.

 

However if I open that design and re-run synthesis and IMP without any changes the design fails timing.


I've verified that the correct implementation strategy (Performance Strategy) is being applied.

 

Can you help out with this issue?

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