We are currently integrating the EVAL-AD6676 FMC Mezzanine with ZedBoard (Mini-ITX / Xilinx Zynq series) Evaluation platform.
The EVAL-AD6676 was purchased through NISKO Projects / Israel.
The SPI core is being implemented as a VHDL block in our FPGA design.
Reading any SPI register content turns to be zero (0x00).
We suspect that there is an error in the electrical schematics (Dwg. No HSC 13039, Rev D):
The direction of the SDIO signal looks to be in the opposite direction (page 6, U13, pins 6 and 9).
Could this be the reason for erroneous reading of the SPI registers?
If yes - Could possible workaround be suggest?