I'm testing on the ADSP-21469 EZ-Kit with DDR2 memory. I've used the DDR2 initialization from the VDSP examples but with CL5. I have a simple delay running on the DSP writing and reading delay samples to the DDR2.
For write access the timing is correct (measuring the DDR2_CS). The time between CS low for write command and next precharge is ~45ns (CL-1 + BL4 + tWR = 4+2+4 = 10 DDR2 clocks at 221MHz).
For reading the time between CS low for read command and next precharge is ~50ns and I don't know why.
I should only have CL + BL4 = 5 + 2 = 7 DDR2 clocks (~32ns).
What did I miss?