To whom it may concern,
Can the DAC8412 VREFH be Tied to VDD? And will this cause any damage to the part? Or will it maybe affect the operation of the DAC8412? Just wondering if it will cause damage.
According to the data sheet, when VREFL + 2.5 V ≤ VREFH ≤ VDD - 2.5 V the DAC8412's operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. Looking at the absolute maximum ratings (Table 3) VREFH to VDD can have 2 V to 33 V difference. Take note that if VREFH is tied to VDD this violates the absolute maximum rating and may cause permanent damage to the device.
One more question:
Can Vlogic be tied to 3.3V? p15 of the data sheet says “It is normally connected to 5V … or left open if unused” … but I couldn’t really tell if 3.3V would also be an acceptable voltage. Do you know?
Looking at the data sheet, there seems to be no problem with it being at 3.3 V as long as the supply can provide enough current to the part for the readback function. Let me verify this internally and get back to you.
So, any progress on this?
The Vlogic pin only powers the digital output circuitry. The Vlogic can be operated at 3.3V, for which the readback will still function but we cannot guarantee the same performance on the digital output levels that we do at 5V, specifically the Logic Output High Voltage and the Logic Output Low Voltage.
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