I just received a AD9361 EVB for the test, and try to implement our new design algorithm with this nice RF board. I am searching the forum and find a simplified hardware reference design in the following link, i.e.
But the very important module in the source code is missing, that is axi_xcomm2ip_core.v.
Without this module, the implementation of FPGA will fail with the follow log:
CRITICAL WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'axi_xcomm2ip_core' instantiated as 'i_system_wrapper/system_i/axi_xcomm2ip/inst/i_core' [c:/Avnet/ad9361_BBP_zc706/hdl/zc706/zc706.srcs/sources_1/bd/system/ipshared/analog.com/axi_xcomm2ip_v1_0/axi_xcomm2ip.v:645]
ERROR: [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'i_system_wrapper/system_i/axi_xcomm2ip/inst/i_core' of type 'i_system_wrapper/system_i/axi_xcomm2ip/inst/i_core/axi_xcomm2ip_core' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
Is there anyone having the full code?