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AD9162 SDO Tri-State, or Not

Question asked by adiup on Mar 17, 2017
Latest reply on Mar 17, 2017 by danf

To Whom it May Concern,

 

In the AD9162 data sheet, CS section on p.43 reads: "The SDIO pin goes to a high impedance state when this input is high."

This description refers to the 3-wire interface. I'm using the 4-wire option and didn't find a similar statement or a timing diagram positively declaring that the SDO output is 3-stated when CS=1. What state is the SDO line when the CS=1?

 

Thank you

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