To Whom it May Concern,
In the AD9162 data sheet, CS section on p.43 reads: "The SDIO pin goes to a high impedance state when this input is high."
This description refers to the 3-wire interface. I'm using the 4-wire option and didn't find a similar statement or a timing diagram positively declaring that the SDO output is 3-stated when CS=1. What state is the SDO line when the CS=1?