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Question about AD6676 output width.

Question asked by success105 on Mar 18, 2017
Latest reply on Mar 20, 2017 by success105

HI,

 

AD6676 is 16-bit IQ output, and the full-scale level is -2dBm, as described in the datasheet.

But when I use it, the  AD6676 output width can not occupy 16 bits, only 13 bits, when connecting with SIgnal Source in -2dBm. The AD6676 output would be wrong when amplifying the input signal power more.

 

The register configuration is listed as below, using "reg_write2(address,value)" to write register. The CLKIN is 61.44MHz, the CLK SYN is enabled, the PHY is  4.9152Gbps. FADC is 2949.12MHz, IF is 138.24MHz, BW is 75MHz, and there is one lane. Is there anything wrong with that?

 

reg_write2(0x0,0x99);        //reset
delay(2000000);                 //delay ms

reg_write2(0x2a1,0xc0);    //clk syn initialization
reg_write2(0x2a2,0x00); 
reg_write2(0x2a5,0x08);
reg_write2(0x2ac,0x30);
reg_write2(0x2b7,0xf0);
reg_write2(0x2bb,0x7d); 
reg_write2(0x2a0,0x7d);
reg_write2(0x2ab,0xc5);
delay(10000);                                
temp3 = reg_read2(0x2bc); 

wait bit1 is equal to 0
reg_write2(0x2ad,0x80);
delay(10000);
reg_write2(0x1e7,0x04); 
reg_write2(0x1c0,0x01);
reg_write2(0x1c1,0x05);
reg_write2(0x1c3,0x00); 
reg_write2(0x1c4,0x03); 
reg_write2(0x1c5,0x07);
reg_write2(0x1ec,0xbd);
reg_write2(0x100,0x85);   //Fadc  is 2949.12
reg_write2(0x101,0xb);   
reg_write2(0x102,0x8a);   //IF is 138.24MHz
reg_write2(0x103,0x00);
reg_write2(0x104,0x4b);   //BW is 75MHz
reg_write2(0x105,0x00);
reg_write2(0x106,0x13);   //ext L is 19nH
reg_write2(0x107,0x0a);
reg_write2(0x108,0x0a);
reg_write2(0x109,0x01);
reg_write2(0x10a,0x40);   //iDAC is 4mA
reg_write2(0x116,0x0a);
delay(2000000);   
temp3 = reg_read2(0x117);  //waiting adjust over

wait bit0 is equal to 1

reg_write2(0x140,0x02);
reg_write2(0x116,0x17);
delay(2000000);
temp3 = reg_read2(0x117);  //waiting adjust over
wait bit0 is equal to 1

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