I am using the AD5685R in a circuit in which I have RSTSEL tied to Vlogic which places the DAC in a midscale output upon toggling the ~RESET pin low. However during testing, when ~RESET is low the DAC output is zero volts then when reset goes high the DAC outputs midscale. Looking at the hardware reset description in the datasheet this behavior seems to contradict what is described.
"~RESET is an active low reset that allows the outputs to be cleared to either zero scale or midscale. The clear code value is user selectable via the ~RESET select pin. When the ~RESET signal is returned high, the output remains at the cleared value until a new value is programmed."
I am wondering if I might have misinterpreted this section or misconnected the DAC. I have attached a schematic with the prototyped output circuit I was using.