AnsweredAssumed Answered

Possible missing feature of Framer Configuration on MYKONOS API

Question asked by yeaten on Mar 17, 2017
Latest reply on Apr 11, 2017 by gverma

I am using ADRV9371 and ZC706 boards and trying to communicate with ad9371.(https://ez.analog.com/thread/92788). Followings are done:

  • AD9528 is fully working.
  • FPGA code is working. 2 lanes Tx - 2 lanes Rx JESD204b cores are implemented and fully functional in near-end loopback mode.
  • AD9371 is working except JESD204b. I mean I can configure AD9371, it is warming up/down when I call radio on/off. Today I managed to link up with Tx lanes.

 

First of all, JESD204b lanes in ADRV9371 are not assigned to ZC706 gigabit tranceivers in-order (I don't know why!).

ZC706 QUADAD9371 Tx laneAD9371 Rx lane
012
130
201
323

Then I assign both jesd204b lanes to the 2nd and 3rd transceivers in ZC706. In this way, I can use 0 and 2 tx serial lanes and 1 and 3 rx serial lanes. My purpose is to try near-end and far-end loopback feature if something goes wrong.

 

I assign 0x05 to deserializerLanesEnabled in deframer and 0x0A to serializerLanesEnabled in obsRxFramer as given below.

static mykonosJesd204bFramerConfig_t obsRxFramer =
{
    0,              /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
    0,              /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/
    0,              /* JESD204B Configuration starting Lane ID.  If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/
    2,              /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
    32,             /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/
    1,              /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/
    1,              /* 0=use internal SYSREF, 1= use external SYSREF*/
    0x0A,           /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/
    0xE4,           /* Lane crossbar to map framer lane outputs to physical lanes*/
    22,             /* serializerAmplitude - default 22 (valid (0-31)*/
    4,              /* preEmphasis - < default 4 (valid 0 - 7)*/
    0,              /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/
    0,              /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/
    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
    1,              /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/
    0,              /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
    0               /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
};

static mykonosJesd204bDeframerConfig_t deframer =
{
    0,              /* bankId extension to Device ID (Valid 0..15)*/
    0,              /* deviceId  link identification number. (Valid 0..255)*/
    0,              /* lane0Id Lane0 ID. (Valid 0..31)*/
    2,              /* M  number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
    32,             /* K  #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)*/
    1,              /* scramble  scrambling off if scramble= 0.*/
    1,              /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/
    0x05,           /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */
    0xE4,           /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */
    1,              /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/
    0,              /* PN inversion per each lane.  bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).*/
    0,              /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/
    0,              /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set*/
    0,              /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/
    0               /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/
};

When I tried to link up the jesd204b lanes, only TX lanes linked up. While I was debugging, I observed that only 1 RX lane enters CGS. Then I was reading UG, I realised that there are crossbars to assign all ADCs to lanes or all lanes to DACs(called serializerLaneCrossbar for RX and deserializerLaneCrossbar for TX). I am digging in and in the function MYKONOS_setupJesd204bDeframer there is a for loop for doing that.

for (lane = 0; lane < 4; lane++)
    {
        if ((device->tx->deframer->deserializerLanesEnabled >> lane) & 1)
        {
            laneXbar |= (((device->tx->deframer->deserializerLaneCrossbar >> (lane << 1)) & 3) << (deframerInput << 1));
            deframerInput += 1;
        }
    }

However if l look up in the function MYKONOS_setupJesd204bObsRxFramer, it does not even loop up the parameter(!). As I understood, it connects lanes by default. 

    if (ML == 42)
    {
        /* uses framer outputs 0 and 2 instead of 0 and 1...fix framer lane XBar */
        /* only 2 lane cases here */
        switch ((device->obsRx->framer->serializerLanesEnabled & 0x0F))
        {
            case 3:
                framerLaneXbar = 0x08;
                break;
            case 5:
                framerLaneXbar = 0x20;
                break;
            case 6:
                framerLaneXbar = 0x20;
                break;
            case 9:
                framerLaneXbar = 0x80;
                break;
            case 10:
                framerLaneXbar = 0x80;
                break;
            case 12:
                framerLaneXbar = 0x80;
                break;
            default:
                /* default to valid setting for Lane 0 */
                framerLaneXbar = 0x08;
                break;
        }
    }
    else
    {
        switch ((device->obsRx->framer->serializerLanesEnabled & 0x0F))
        {
            /* all 4 lanes get framer 0 output */
            case 1:
                framerLaneXbar = 0x00;
                break;
            case 2:
                framerLaneXbar = 0x00;
                break;
            case 3:
                framerLaneXbar = 0x04;
                break;
            case 4:
                framerLaneXbar = 0x00;
                break;
            case 5:
                framerLaneXbar = 0x10;
                break;
            case 6:
                framerLaneXbar = 0x10;
                break;
            case 8:
                framerLaneXbar = 0x00;
                break;
            case 9:
                framerLaneXbar = 0x40;
                break;
            case 10:
                framerLaneXbar = 0x40;
                break;
            case 12:
                framerLaneXbar = 0x40;
                break;
            case 15:
                framerLaneXbar = 0xE4;
                break;
            default:
                /* default to valid setting for all Lanes */
                framerLaneXbar = 0xE4;
                break;
        }
    }

In my opinion, if serializerLanesEnabled=0x0A / b1010, serializerLaneCrossbar=0xE4, framerLaneXbar should be 0x0D. What am I going to do if I want to assign obs. rx outputs to the 1 and 3 lanes?

Outcomes