The enable0 and enable1 signals were low coming out of the ad9144_core IP and that was preventing data from flowing out of the ad9144_upack IP. Customer seeing data going into the upack IP with an ILA, so rebuilt an image that had the enable0 and enable1 at a constant "1". In this scenario the data looks good out of the 9144_upack but nothing is coming out of the 9144_core IP. It‘s not obvious what drives the ad9144_core IP to trigger the enable signals and output data itself. What determines this? What would prevent it from letting the data be passed through? The clocks are running internal to the FPGA at the expected frequency, the JESD clocks (serdes and sysrefs) are running at expected frequencies. All the resets look right as well.