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DAQ2: how to change JESD lane rate

Question asked by Chris449 on Mar 17, 2017
Latest reply on Mar 22, 2017 by Chris449


I made a pcb using a similar setup of daq2 except that I replace AD9144 by AD9136 and AD9680-1000 by AD9680-500.

On the FPGA, I am using your reference design (hdl_2015_r2).

Since the configuration is the same, I can make the DAC to work.

However, for the ADC, since I am using the AD9680-500, I need to change the lane rate compare to your DAQ2.


Here is teh configuration I would like to run:

- DAC_CLK=ADC_CLK=491.52MHz instead of 1GHz


- M=2, L=4


It means that the lane rate will not be around 10Gbps anymore but 5Gbps. For the AD9523, I know how to set it up.

Please could you tell me what I have to change in the fpga reference design?


I tried to follow these to threads but was kind of lost. 

How do you reduce the effective sampling rate of the DAQ2 noOS project for the KCU105 with analog JESD204B? 


Thanks a lot.