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AD9517 external loop filter on AES-PZSDRCC-FMC-G

Question asked by xiaoyur on Mar 17, 2017
Latest reply on Apr 5, 2017 by xiaoyur

We have the PicoZed (SDR) Development Kit (AES-PZSDRCC-FMC-G). The AD9517 in the FMC Carrier can not be locked.

Our final purpose is to get the clock of 212.5MHz, and we find that the footprint of REF1 has a clock of 25MHz, and REF2 is not used. We set the R divider equal to 1, so the PFD frequency is 25MHz. And we set the internal VCO is 2125MHz. The external loop filter in the Carrier as follows. I am confused that the PLL is unlocked, and I guess it is because of the insuitable of PFD frequency and internal VCO for this loop filter.

Now, we set R=1, P=8(DM), A=5, B=10. Internal VCO Divider=2, Channel Divider=5.

I want to which frequency should be setted of the PFD frequency and internal VCO!

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