I have a question about ADV7181D.
What will happen if signal input to AIN when AVDD = 0V?
Would the device break?
Q1) Keeping Ain to the numbers listed in the Absolute Max Table will keep the input safe.
Q2) Yes, this is correctQ3) Normally a bridge diode can be connected right at P5. The problem with this is if the CVBS input has a negative offset then the sync might be clipped causing loss of lock.. The only other option is to place place the bridge diode after the decoupling cap.
Now our reference board does not use a bridge diode or any other type of protection and has not seen any failures. Again looking at the scope I don't see any clipping meaning the chip ESD protection has not kicked in. This also means the Ain gate oxide can handle normal CVBS amplitudes without problems as the reference board does. The absolute max rating is related to continuous current flow and not necessarily the spikes we/d swee from a CVBS source.
Your question is forwarded to the part specialist.
Ain is a high impedance input and normally DC decoupled from the source. If the ADV7181 is powered down then the source will just see a 100nF load plus ESD protection on the analog signal. This should not cause a damage to the ADV7181
Thank you for you advice.
Can you say same thing to other devices?
For example, ADV7180, ADV7281-M ADV7481.
I believe their reference designs are DC decoupled also so the basic load in powered off state would be the same. Keep in mind that the ESD structure will be different for each device and you may get different responses.
I need to back off my previous statement a bit. The ESD structure has to be able to handle the dv/dt energy of the analog video signal after it goes through the decoupling cap. The ESD structures were not designed to handle this so over time there might be some degradation. The best solution might be to add a bridge diode to limit the amplitude range that the device sees.
Thank you for your reply.
Actually my customers question is this.
=> At their application, input comes before ADV power up.
The voltage is 1Vpp.
Would it be problem?
So I'm asking to my customer, is the input comes to the coupling cap or ADV.
Also if the input comes to ADV, what is the voltage value from ADV GND.
Anyway I measured this with ADV7181D eval board.
When ADV7181D is power off(AVDD=0V), AIN1 input will be -0.6V to 0.5V.
Would this break ADV7181D?
Thank you for you support.
Can you give some advice for the newest question?
looking at the yellow trace I don't see the ADV7181 ESD protection going active at all. This should be safe for the ADV7181.
For production are they adding any input ESD to the CVBS signal?
Just some factoids:
1) ESD damage can be caused by over voltage burning through the input gate oxide layers. ESD protection is meant to stop these over voltage conditions without impacting the impedance path under normal operating modes.
2) ESD protection can be burned out when it has to shunt excessive energy from the source. Normal ESD hits can't do this, repetitive hits can cause problems. Strictly a thermal issue. With the decoupling caps this would be also impossible to do.
So the damage to an input pin can be caused by over voltage blowing through the gate oxide or excessive repetitive energy hits.
No, the yellow signal is just a CVBS source signal.
The AIN pin signal is blue one as I wrote to the circuit which I attached.
We have never heard about ESD circuit so I will check it.
So you mean our customer have to keep AIN voltage to AVDD±0.3V?
If AVDD = 0V, is the AIN absolute maximum -0.3V~0.3V?
To protect this should our customer add kind of ESD diode?
If they should , where should they add?
AIN to AVDD ?
Which document are you talking about "Normally a bridge diode can be connected right at P5"?
No specific document. It is used on other reference platforms. Standard circuit analysis will show how to limit the voltage to the Ain pin. Only edges can cross the decoupling cap to cause over voltage spikes so if you limit the edge voltages, you will limit the voltage the Ain pin sees.
I couldn't understand "right at P5".
What did you mean?
What is "Standard circuit analysis"?
Can you show us the circuit how to limit the voltage?
Q1) Right next to the P5 connector on the board, where the signal comes in
Q2) You just want to make sure the video signal is not clipped, specially the sync pulse
Q3) Assuming the source is ground referenced and not floating.
I got it
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