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ADV7842 Output Timing Specifications

Question asked by DRC on Sep 23, 2011
Latest reply on Sep 26, 2011 by DaveD



In the ADV7842 datasheet, the timing specifications for the video output pins are shown in Table-5 and Figure-5.  I'm using the CP timing numbers.  The timing is specified relative to the falling edge.


In particular, the parameter t14 specifies the time between the negative clock edge to the start of valid data.  This seems to imply that the ADV7842 outputs data on the falling-edge of the clock.


However, when I probe the data pins on the scope, the data transitions much earlier, seemingly on the rising-edge of the clock.  It's much earlier than specified in the datasheet.  I've attached a scope shot of what I'm seeing (yellow is LLC pin N1, purple is P2 pin B3).  Why doesn't the data change near the falling-edge?  Or can you tell me what the specifications should really be?


The ADV7842 feeds an FPGA.  I used the numbers from the datasheet in specifying the input timing constraints on the FPGA, so I need these to be correct.


I have not tried playing with the LLC DLL so it's disabled by default.