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question about 21489 connect ad1933

Question asked by Graydon on Mar 9, 2017
Latest reply on Mar 29, 2017 by Jithul_Janardhanan

Hello, I want to use AD1933 as slave, it connect with ADSP21489.  In ADSP21489, I use PCGA generate CLK(3.072M) and frame sync clock(48k) to AD1933. And I send a sinusoidal signal, but the AD1933 output pin have not ideal output, it is discontinuous, look at the piecture 1. But I changed AD1933 as master and ADSP21489 as slave, the ad1933 output is pure sinusoidal signal. 

I don't know what 's happened. 

I pushed my code pieces, someone help me to look what wrong, thanks.

situation for ADSP21489 slave, AD1933 Master:

unsigned char ConfigParam1939 [] = {
(AD1939_ADDR), DACMUTE, 0x00,
(AD1939_ADDR), CLKCTRL0, DIS_ADC_DAC | INPUT256 | PLL_IN_MCLK | MCLK_OUT_OFF | PLL_PWR_DWN,
(AD1939_ADDR), CLKCTRL1, DAC_CLK_PLL | ADC_CLK_PLL | DIS_VREF, //////1

#ifdef USE_48_KHZ_SAMPLE_RATE
(AD1939_ADDR), DACCTRL0, DAC_FMT_I2S | DAC_BCLK_DLY_1 | DAC_SR_48K,
#endif
#ifdef USE_96_KHZ_SAMPLE_RATE
(AD1939_ADDR), DACCTRL0, DAC_FMT_I2S | DAC_BCLK_DLY_1 | DAC_SR_96K,
#endif
#ifdef USE_192_KHZ_SAMPLE_RATE
(AD1939_ADDR), DACCTRL0, DAC_FMT_I2S | DAC_BCLK_DLY_1 | DAC_SR_192K,
#endif

(AD1939_ADDR), DACCTRL1, DAC_BCLK_MASTER| DAC_LRCLK_MASTER| DAC_CHANNELS_2 | DAC_LATCH_MID | DAC_BCLK_SRC_PIN, //2
(AD1939_ADDR), DACCTRL1, DAC_BCLK_MASTER| DAC_LRCLK_MASTER | DAC_CHANNELS_2 | DAC_LATCH_MID | DAC_BCLK_SRC_PIN, //Ddebug

(AD1939_ADDR), DACCTRL2, DAC_WIDTH_24 ,


//(AD1939_ADDR), AUXCTRL0, AUX_LATCH_MID | AUX_FMT_I2S | AUX_BCLK_DLY_1 | AUX_WIDTH_24,
//(AD1939_ADDR), AUXCTRL1, AUX_BCLK_SRC_PIN | AUX_CHANNELS_2 | AUX_LRCLK_FMT_50_50|AUX_LRCLK_POL_NORM|AUX_BCLK_POL_NORM, // NDdebug

(AD1939_ADDR), DACVOL_L1, DACVOL_MAX,
(AD1939_ADDR), DACVOL_R1, DACVOL_MAX,
(AD1939_ADDR), DACVOL_L2, DACVOL_MAX,
(AD1939_ADDR), DACVOL_R2, DACVOL_MAX,
(AD1939_ADDR), DACVOL_L3, DACVOL_MAX,
(AD1939_ADDR), DACVOL_R3, DACVOL_MAX,
(AD1939_ADDR), DACVOL_L4, DACVOL_MAX,
(AD1939_ADDR), DACVOL_R4, DACVOL_MAX,

(AD1939_ADDR), CLKCTRL0, DIS_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_XTAL | INPUT256 | PLL_PWR_UP,
(AD1939_ADDR), CLKCTRL0, ENA_ADC_DAC | PLL_IN_MCLK | MCLK_OUT_XTAL | INPUT256 | PLL_PWR_UP,

(AD1939_ADDR), DACMUTE, 0x00,
} ;

Above config AD1939, it works fine. 

 

And I change it to slave, just change a little like this, note that the red area.

.....

AD1939_ADDR), DACCTRL1, DAC_BCLK_SLAVE| DAC_LRCLK_SLAVE| DAC_CHANNELS_2 | DAC_LATCH_MID | DAC_BCLK_SRC_PIN, //2
(AD1939_ADDR), DACCTRL1, DAC_BCLK_SLAVE| DAC_LRCLK_SLAVE | DAC_CHANNELS_2 | DAC_LATCH_MID | DAC_BCLK_SRC_PIN, //Ddebug

.....

 

and code piece in DSP:

 

int reg=0,r0,i;
int fs_div = MCLK/RATE_SAMPLES;
int sclk_div = MCLK/(RATE_SAMPLES*32*2);

 

* pPCG_CTLA1 =0 ; *pPCG_CTLA0 =0;
for(i=0;i<10000;i++);//delay

//*pPCG_PW = 32*2;


r0 = sclk_div | CLKASOURCE | FSASOURCE | ((sclk_div/2)<<20) ;
*pPCG_CTLA1 = r0 ;

r0 = fs_div ;
*pPCG_CTLA0 = r0;

r0 = ENFSA | ENCLKA ;
*pPCG_CTLA0 |= r0;

 

config PCGA  , it worked. But the ad1933 output is not normal. 

So I want to know if I config AD1933 as slave mode correct? 

if right, it it must be pcg clock is wrong, how to do it?  

Also I have a question about phase shift, I don't know why there is ((sclk_div/2)<<20), I just do it as looking at datasheet. if someone explain it to me , I am very appreciative!

 

 

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