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AD7763 - FSO, SYNC, MCLK Signals

Question asked by KaiserSozze on Mar 8, 2017
Latest reply on Mar 21, 2017 by KaiserSozze

Hi Guys, 


Just need some info on what signals are absolutely necessary for intefacing to a pair of daisy chained AD7763s, with an FPGA - in this application we are a little restricted on IO. 


1. Is it necessary to use the SYNCn pin, is it the same (or better) to send send the sync command via SPI (by setting the sync bit). This way all adc's get the sync command synchronous to MCLK? Can we have the SYNCn pin pulled up via a resistor and send the SYNCn command via SPI only. 


2. Currently we have interfaced successfully to the ADC using an FPGA, the state machine inside uses the DRDYn signal to start shifting in data from the pair of ADCs (ADDR 000, 001). We do not use FSO from either of the AD7763s, as the serial data is of a fixed predictable length, syncronous to SCO and appear 1 cycle after DRDYn goes low.


In this situation, is it fine to not use FSO, is there any reason why we must?


3. MCLK, as per our interpretation of the datasheet we are using a digital IO voltage of 2.5V and MCLK of 5V. Is this correct, MCLK voltage can be higher than digital IO, do any other rails also have to be 5V for MCLK to be 5V. 


Thank you guys, just getting started we have high hopes for this part !!