I'm looking at the LATCH pin in AD8561.
It seems like LATCH logic threshold values are strange.
For example, LATCH pin Logic "0" (TYP) should be less than (MAX).
But, Datasheet shows (TYP)=1.6V, (Max) = 0.8V
Could anyone explain that?
If you strictly look on the voltage values, yes the Logic "1" threshold should be in Max column while the Logic "0" threshold should be in Min column. What the data sheet is trying to say is that, to ensure that latch pin has a Logic "1" input across operating conditions, you should have a minimum of 2V. Meanwhile to ensure that latch pin has Logic "0", the voltage should be maximum of 0.8V.
Thanks and best regards,
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