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What could be cause of higher (wrong) baud rate after I switch the master clock?

Question asked by dinrail on Mar 7, 2017
Latest reply on Mar 8, 2017 by ABuda

To sync several AduCM361s together, I need to clock them with the same master clock, which was fed into the micro via ECLK pin:

    DioCfgPin(pADI_GP1,PIN0,2); //configures P1.0 as  EXT CLK IN
    ClkCfg(CLK_CD0,CLK_P4,CLKSYSDIV_DIV2EN_DIS,CLK_UCLKCG);

    ClkSel(CLK_CD0,CLK_CD0,CLK_CD0,CLK_CD7);     // Select CD0 for UART System clock

 

Every thing seems to run fine until recently, I run into problem

 

About half the time, after I switch to the external clock, the UART will output at much higher baud rate (about 5 times higher), even after I placed some delay after the switch and re-initialize UART to the desired baud rate

 

Any pointer at where I should look into this problem?

 

Thanks!

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