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PLL issues with ADSP-21479 EZ-Board

Question asked by matthiaswe on Mar 7, 2017
Latest reply on Mar 29, 2017 by Jithul_Janardhanan

Hey there,

we got an ADSP-21479 EZ-Board. As we want to do some profiling/benchmarking, we want to make sure that the processor is running it a relatively high clock frequency.


The debug output of the bootloader located in NAND flash is:

*** 21479 EZ-Board Power-On Self-Test


Built on Feb 15 2010, at 14:29:34

Built for rev 0.1 EZ-Board

Configured PLL for 266 MHz CCLK, 133 MHz SDRAM clock


However, when connecting with the Standalone Debug Agent and waiting at the breakpoint when entering main the value 0x5 is read for PMCTL which refers to a PLLM value of 5 and a PLLD value of 0.

The f_CCLK should then calculate as (2 * 5 * 16.625 MHz) / 1 = 166.25 MHz which is not the expected CCLK of 266 MHz (assuming my calculations are right).


When compiling and running the POST example in CCES the value changes to 0x10 for PMCTL after a call to

Init_PLL(). As consequence I updated the bootloader in the NAND flash. But still: the value read by the debugger from the PMCTL register is reset to a value of 0x5 when entering main(). I made sure that the new bootloader is flashed, see debug output:

*** 21479 EZ-Board Power-On Self-Test


Built on Mar 6 2017, at 09:30:50

How is the value overwritten? I think it cannot be the boot kernel, as this is already executed before the application code calling Init_PLL(). Is there some interference in the debug process, e.g. is there an init script run when connected via JTAG / the Standalone Debug Agent?


A possible solution would be to copy the Init_PLL() code to my application code but can I make sure that the CCLK is kept high when in debug mode? Furthermore, the CCLK cannot directly be measured directly - is there any code readily available to use a peripheral with a fixed divided clock frequency to supervise the PLL settings?


Thank you in advance!


Kind regards,