I'd like to use directly through CLK± (bypassed DACCLK).
Which registers should I set to bypass PLL circuit?
The internal on-chip DAC PLL can be bypassed by writing Register 0x83 Bit 4 = 0. Then the AD9144 should get a clock signal directly at the DAC frequency desired for the update rate on the CLK+/- pins. If you wish to use the internal PLL Register 0x83 Bit 4 = 1 and the reference clock for the PLL should be sent to the CLK+/- pins instead.
hi,MicheleV ,can you give me a config sequence for ad9144 DC TEST Mode?
If you are not using the DAC PLL (PLL doesn't have to be configured) you can use the following sequence following the first 2 tables of the Device Setup Guide for initialization and then just enabling the DC test mode and configuring the NCO and DC amplitude:
0x000 0x00 or 0x18 for 3 wire or 4 wire SPI depending on your setup
0x011 0x00 (if using all 4 DACs, otherwise can choose to power down unused DACs in bits [6:3]
0x146 0x00 (this is the setting for DC test mode, for normal SERDES operation mode you would use 0x01)
0x008 0x03 (page both dual DAC pairs to write the same values, you can choose to only set one dual pair at a time if you want two different tones, one for each dual pair)
0x520 0x1E (set bit 1 to 1, keep other bits to default)
0x521 Set the I data LSB of the desired DC amplitude of the tone (0xFF for full scale)
0x522 Set the I data MSB of the desired DC amplitude of the tone (0x7F for full scale)
0x523 Set the Q data LSB of the desired DC amplitude of the tone (note that I and Q must be complex, so often this is just set to 0x00)
0x524 Set the Q data MSB of the desired DC amplitude of the tone (same note as before, likely set to 0x00)
0x112 0x04 Enable NCOs for modulation
0x114-0x119 set the FTW for the desired frequency of the tone you want
0x113 0x01 Update the FTW word to take effect in the part
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