The DAC Latency does not match the specification in the datasheet:
The DAC was chosen because of its low latency. When our board is ready the latency appeared to be 14 cycles that is exactly twice vs. latency in datasheet (7 cycles).
Please find an oscilloscope figure attached.
DAC sampling and data clock was 200MHz. A saw signal data was generated on FPGA for both I and Q channels simultaneously. Oscilloscope C1 probe was connected to IOUT1P (U5-69), C3 differential probe to DCI pins (U5-29,U5-30) and C4 differential probe to D11 pins(U5-9, U5-10). (U5 is the AD9780 in the schematic not attached)
The MSB bit changes are uses for trigger setup the measurement.
The experiment was repeated at 400 Msps with the same result. Latency was 14 cycles.
Please could you please tell me whether I’m doing something wrong or I it’s a mistake in datasheet. Thanks.