For the ADF4158 3.3V logic operation and for ramp generation,
what are the minimun Txdata Low and High times, respectively?
The txdata input must meet the timing shown in Figure 3 on page 7 of the datasheet. No hold time is required therefore the minimum high time is the same as the setup time -- 10ns. This rising edge on this input is used as an interrupt to latch the current ramp frequency. There is no minimum low time but insure the signal is driven to a valid logic low (<0.6V).
I would apprecite it if someone would advise of this.
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