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AD9234 - PRBS Pattern Testing

Question asked by Rekha on Mar 2, 2017
Latest reply on Mar 6, 2017 by UmeshJ



I'm able to receive JESD Test mode patterns in FPGA board successfully. Since we are able to receive data, we are working on traffic test. 

When we configure PRBS 7 at both ADC board and Kintex 7 board, we observe no link and high BER. Even though link is not up, FPGA can detect the eye. Please let me know if there is any ADC configuration setting to get 0 BER and link up. 

Configuration: 10Gbps, Reference clock = 250MHz