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Failed at MYKONOS_checkPllsLockStatus

Question asked by yeaten on Mar 1, 2017
Latest reply on Mar 7, 2017 by gverma

I have been working with ADRV9371 & ZC706 boards and I am trying to make ad9371 work with bare metal app. Also I am aware of following topics.


What have I done so far is:


  1. Zynq processing system with all peripheral interfaces including JESD204B and all discrete IOs
  2. I completed common.c file from older API (using API 3534.0 - TES v2056).
    1. Both hard resets are working.
    2. I can communicate with both ICs via SPI
    3. All discrete IOs(tx/re enables, resets, sysref_req etc.) can be controlled via Zynq
  3. I created myk_init and ad9528_init.c structures via TES.


But I have face some problems and I have following questions:

1. We have tested ADRV9371 with TES application but we did not used external REFA input. But while I was testing ad9528 with bare metal application it stucked at initialization. My initialization sequence is:


adi_status = AD9528_resetDevice(&clockAD9528_);



adi_status = AD9528_initialize(&clockAD9528_);

When I look at the register map of AD9528, it is not possible to see 0x27 at reg0x508 because I have not applied REFA input. However, even if we don't applied REFA input, we can see 122.88MHz on the outputs. Is it ok to bypass the PLL1 on the AD9528 and skip the "REFA" and "PLL1 lock check" status in the reg 0x508?



2. We applied 30.72 MHz to the REFA input and AD9528 initialized properly. But this time after the initialization of AD9371 (MYKONOS_initialize(&mykDevice)), it stucked at CLKPLL lock check (MYKONOS_checkPllsLockStatus(&mykDevice, &pllLockStatus)). It returns 0x02 and as far as I understand only RX PLL is locked instead of CLKPLL. What could be a problem? (MYKONOS and AD9528 API or myk_init and ad9528_init files generated by TES are unmodified.)


After CLKPLL lock check I inserted proper MYKONOS_setRfPllFrequency/MYKONOS_getRfPllFrequency functions but I failed to read the correct data. (Update: As I understood, RF PLL are only be set after arm initialization and if I try to read the CLK PLL frequency, it returns ~66.8 GHz :/ )


3. Everybody says TES creates required configuration for ADRV9371 but there no fully working template. For example I can not close both RX1 and RX2 inputs or OR1/2 or SNIFFERA/B/C. I can not select the PLL of ORx. Is it ok or enough to edit required places in the myk_init file for those.  Also header.c file has missing places such as

  • AD9528 initialization sequence. TES only creates required data structure.
  • Before the MYKONOS initialition there are lines for example,

/*** < Action: Insert System Clock(s) Initialization Code Here > ***/

/*** < Action: Insert BBIC Initialization Code Here > ***/

Does it mean AD9528 or is it the cause of question 2?


And there is a bug in TES (v2056), it creates agcRx2MaxGainIndex parameter twice in the obsRxAgcConfig structure in the myk_init.c file.


4. Why AD does not provide register map of AD9371?