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Multichip Synchronization for 4x4 MIMO

Question asked by cellguy on Feb 28, 2017
Latest reply on Mar 3, 2017 by Vinod

The user guide has a section on multichip synchronization for 4x4 MIMO on page 53. However, I don't see magnitude and phase uncertainties specified in the datasheet. What are the specifications for these multichip uncertainties from:

Internal or external Tx LO (starts with divide by 2 uncertainties)

Internal or external Rx LO (starts with divide by 2 uncertainties)

Input RXn+/- pin to ADC

Clocking of the ADC from DevClk

DAC to TXn+/- output pin

Clocking of the DAC from DevClk

ADC to JESD204B serial pins

JESD204B serial pins to DAC

SerDINx+/- to TXn+/- pins

RXn+/- to SerDOUTx+/- pins

Clocking of the JESD204B interface from SysRef

JESD204B serial links especially across multiple lanes

Is synchronization across multiple JESD204B serial links always deterministic?

SYNCIN to ADC data on SerDOUTx+/- pins

SYNCOUT to SerDINx+/- data on TXn+/- pins

DDC

Group delay through tunable LPF at various frequencies and settings.

Any other sources?

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