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Question asked by pinkpanther on Feb 28, 2017
Latest reply on Mar 13, 2017 by pinkpanther



I am using AD9361 with ADI provided IP core in Xilinx Zynq 7020 device, and am working on timestamping the blocks on rx and tx paths. 

There are four blocks that the axi_dmac uses.

Talking about the RX side, I am using the simple approach:


1. I have four memory-mapped registers (Buf0, Buf1, Buf2, Buf3)  for four RX blocks

2. Whenever the DMA is enabled and and the data valid signal (adc_dvalid from axi_ad9361 core) are high, I put the timestamp on the Buf0, 

3. I monitor the X_Lenght register, using count-down counter. When it is done, I put the timestamp on the 2nd register (Buf1)

4. Repeat step 3 for the rest registers, Buf2, and Buf3. 

5. Keep going as long as DMA and/or Timestamp in enabled. 


Is this simple approach going to work?


I am concerned about synchronizing my timestamping  and the axi_dmac (along with the software).


Can you please advise if I need to monitor additional signals from axi_ad9361 and/or axi_dmac cores)?


Thank you for your suggestions. 


Best regards.