I tested a general purpose timer on my Blackfin 527. The timer toggles a pin at a regular basis. I just wondered how much time it takes the pin to change state. Then I started to analyse the individual instructions in the debugger and I found that instructions on my Blackfin 527 executed a way much slow.
Let’s see the following c-line:
*pTIMER_ENABLE = TIMEN7;
That is compiled into:
P1 = 1664 ( X ) ;
P1.H = 0xffc0 ; // P1 = TIMER_ENABLE
R0.L = 128 ; // R0.L = TIMEN7
W [ P1 ] = R0.L ; // *pTIMER_ENABLE = TIMEN7
P1 = 1664 ( X ) ; takes 10 CCLK cycles to execute.
R0.L = 128 ; takes 23 CCLK cycles.
These are measured with the CYCLES register.
How is it possible? Or what I’m missing here?
I have a BF527BBCZ-5A on a proprietary board, CLKIN=25MHz, CCLK=525MHz, SCLK=43.75MHz
My program runs from L1 memory.
I understand that the TIMER_ENABLE register is a system MMR. It is in the SCLK domain and Peripheral Access Bus has a latency of 2 SCLK cycles. However, access to P1 and R0 should execute in 1 CCLK, shouldn’t?
So what is the point I am missing?
I measure the execution time with the Performance Monitor Unit too (PFCNTR0 and PFCNTR1 registers). That results similar execution time.
PFCNTR0 is set to “Processor stalls to memory”
PFCNTR1 is set to “Code memory fill stalls”
P1 = 1664 ( X ) ; results --> PFCNTR0=6, PFCNTR1=8