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2.5MHz CLK rate for AD7124?

Question asked by slastuka on Feb 27, 2017
Latest reply on Mar 5, 2017 by JellenieR

Inquiry Description:
We are using an external 625KHz clock on the CLK pin to drive the AD7124 modulator in high power mode.  We see that the CLK_SEL bits in the ADC_CONTROL_REGISTER should be set to 0b10 for an external clock.  However, there is an option discussed in the datasheet for a divide by four (0b11) that implies we could put in a 2.5MHz clock.  What is the point of the divide by four?  Is there an advantage if we use it? 

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