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How to control REG_CHAN_CNTRL_7 (DAC_DDS_SEL)

Question asked by ma3001240 on Feb 27, 2017
Latest reply on Apr 10, 2017 by ma3001240


On the PicoZed board, I have an FPGA-based algorithm that is controlled by a python script running on the PS in the Linux distribution supplied in the example design.  I am attempting to control the AD9361 via the python script, and have had great success with most parameters via /sys/bus/iio/devices.  However, the system seems to start up with the DAC outputting from the internal DDS, instead of taking data from the datapath on the FPGA (which, in the software, ends up being called DMA Data, I believe).  I can't find this control in /sys/bus/iio/devices, and have been unsuccessful trying to control it via /sys/kernel/debug/iio/iio:device0/direct_reg_access, which seems to be the recommended alternative.



  1. What is the best way of controlling the DAC_DDS_SEL parameter from the shell or from python?
  2. How do I translate the information in the register map on the wiki to the address I need to feed to direct_reg_access?
    1. For example, the register REG_CHAN_CNTRL_7 is at address 0x1106 (32 bit word) or 0x4418 (byte).  What type of access is direct_reg_access using?
    2. Reading through some of the C code, it looks as if there are several offsets that need to be determined as well.  Possibly a base device offset, an offset to the DAC register base, and an offset to the channel base.  How do I determine these?


Thanks much!