In case that Vgg1 is pre-adjusted and fixed by register divider, is following sequence no problem?
The biasing sequence:
A) Set Vgg1 (Idq adjusted voltage, fixed to somewhere between -2V and 0V)
B) Set Vdd to +8V
C) Set Vgg2 to +3V
My customer understands recommended biasing sequence described in https://ez.analog.com/docs/DOC-11963, however, from circuit size point of view they would like to apply fixed voltage to Vgg1 by resister divider.