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BF707: wrong SMC behaviour

Question asked by al.ex.us on Feb 23, 2017
Latest reply on Mar 15, 2017 by al.ex.us

SMC generates a garbage transactions under some conditions, easily reproducible but absolutely not understandable!

Look at the code:

 

for (;;)

{

   *(unsigned*)0x70000008 = 0x12345678;

   // ssync ();

   *(unsigned*)0x7000000C = 0x77777777;

 

   pause_microsec (1000);    

}

 

When ssync() between writes is commented out, I see an excess transactions on the bus.

Blue is AMS, yellow is AWE.

We can see the first 32-bit write - 2 AWE pulses, but the next write gives 4 AWE pulses, which is wrong

(remember that the bus is 16 bits wide).

 

 

With ssync() inserted, everythyng is always OK:

 

 

The further the more strange:

this behaviour depends on the particular addresses! (Even though they all aligned by 4!!)

For example if the second write is to 0x70000010 or 0x7000001C, it looks OK!

 

Any thoughts?

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