We are trying to run the ADDI7004 with little success of just trying to power up the device and getting a LVDS TCLK out of the part.
So far this is what we have done..............
We follow the recommended power-up sequence found on page 34 to the letter.
Some of the supporting information:
1. The CLI clock is running at 10MHz (which was noted by AD that it is the slowest speed that the part can operate).
2. The SPI clock is running at 1MHz.
3. The SPI address and data are sent LSB first as noted on page 38 and confirmed in real time with an logic analyzer.
4. Both VD and HD are held high during the power up sequence as shown in figure 61 on page 34.
Once the recommended power sequence is completed the falling edge of both VD and HD go low at the same time during the falling edge of CLI and should be latched in by the AFE part during the rising edge all within one clock cycle as noted on page 35 figure 61.
What are we missing??????