what is the total current of VDDA_RXSYNTH and VDDA_TXSYNTH ?
thanks for answering.
Please refer https://ez.analog.com/message/266426
i have another details in the ADRV9371-W_PCBZ_Schematic_RevA.pdf, resistors R709 and R710 enable the chnnel 3 first, but the VDIG need to be enabled firstly, the sequence seems not correct, why?
ADP5054_EN signal will enable ch2 which is VOUT2_1V3_DIG(VDIG) and then 1P3_BUCK_OUT(VOUT2_1V3_DIG) enables ch1(VOUT1_1V3_ANLG) and ch4(VOUT4_1V8).
ch3 is VOUT3_3V3 not VDIG
but i think FMCA_VCC_12P0V will enable the chn3 by R709 and R710, before the ADP5054_EN pin enables the chn2 (VDIG).am i right?
CH3 output gets enabled at last as highlighted below, the PWRGD pin is an open-drain type output and it allows you to perform logic AND operation, The register divider provides a weak pullup.
The default PWRGD setting for ADP5054 is monitor CH1.
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