I have a customer, Vanteon, who is having trouble getting past the CGS state in the JESD interface when connecting the AD9371 with a Xilinx FPGA.
Note that they are trying to get the Tx side of the AD9371 running, so the FPGA is the JESD transmitter, and the AD9371 is the JESD receiver.
They are asserting the sync signal (sync = low) and they are seeing the K characters generated on the JESD lines from the FPGA. However, the sync line is not de-asserting itself.
Can you please give me a short list of possible problems that could lead to trouble getting out of the CGS phase in the JESD interface?