after synchronization of small UE design RX path to UMTS CELL the big random phase error is observed.
Phase jumps for +-PI over each 38400 chips while frequency is well synchronized.
What are the ways to clean phase using 9361?
What is the receive input power level and Rx gain when you are seeing this issue. Can you check this at -70dBm input power?
unfortunately the phase dances still here even with 65dB RSSI
problem is still present
" Phase dances" , are you observing a 180Deg shift or random phase shift.
How are you measuring phase ?
Please see below few related posts.
I calculate CPICH after descrambling and despreading and see it is significantly drifting up to 180deg and back hundred times per second. But PLL frequency is well synchronized according to Sync channels.
Can you read back the gain when you see this issue?
Change the AGC mode to manual and set the same gain and try.
From Above we cannot comment much.
Can you try measuring EVM ?
Alternately if you can check by giving a Test model waveform from generator and check .
Now I think temperature fluctuations lead to phase dancing
I see that +-1 gradC correspond to 1ppm
This is what I actually see
Do you use temperature stabilizator for tests?
No we don't use temperature stabilization .
Can you try disabling tracking cals.?
If you are able to Sync the signal and demodulate same , then RF phase change may not be your issue.
Here is CPICH phase in Deg example over second period while PCH and SCH are fully sync
Looks like I've missed something but I ran out of ideas
I think there are two problems:
1. small error of frequency synchronization can lead to CPICH modulation (shown on fig)
2. when phase distortion occur I see synchronization error +- 1ppm per second
I need to learn them separated
Again, may be there is good way to synchronize PLL to clock extracted from air?
I think you need to have a AFC implemented in your system to track clock extracted from air.
It can be done on AD9361 using the DCXO feature of chip, for more details refer below link
Tuning the AD9361/AD9364 [Analog Devices Wiki]
I dont believe DCXO could be synchronized well because of its graduality.
Looks like there are two ways:
1. Synchronize PLL (not realized)
2. Do drift compensation in software (in progress)
Retrieving data ...