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about the timing sequence stablility of ADV7619 output

Question asked by WilliamLian Employee on Feb 21, 2017
Latest reply on Feb 27, 2017 by JeyasudhaMuthuPerumal

Refer to ADV7619 datasheet, the time sequence of LLC and data output is as below


feedback from a customer, when input is from 4kx2k camera, output LLC freq is 148.5MHz, the timing sequenc of LLC and P0 to P7, HS,VS/FIELD/ALSB, DE is different among differnt parts. below two figures got from two parts in just same board and environment.


figure 1

figure 2


customer want to get ADI's reply which one timing sequence is the expected one,  and does this means the other one is over specification?  or you think both of these two figure reprensent normal ADV7619

there's big timing diffference between the 2 parts, is there any possiblility that other parts with more timing sequence difference?

 if customer need adjust the LLC_DLL_PHASE[4:0] register to ensure the output stable, need refer to figure 1 or figure 2 or other information?