I'm currently working on a PLL design that's to generate frequencies from 12 GHz to 20 GHz.To do so, I'm using a HMC733 VCO with a HMC704 PLL (with a HMC447 div-by-4 to feed the VCO reference back to the PLL). After tweaking the loop filter, I finally got the PLL to lock throughout the frequency range I wanted, with one drawback: I'm noticing that the noise floor rises on both sides of my carrier signal as shown below:
The SpecAn capture I show is for a 16 GHz VCO output. This behavior is present throughout most of the frequency range of operation of my design (12 GHz up to ~18 GHz). Any thoughts on what might be causing this? I've tried increasing/decreasing the loop filter BW but this behavior persists. I'm currently using an 3rd order active C loop filter, with a 500 KHz loop filter bandwidth and a 80 degree phase margin. Also, both the VCO and the div-by-4 are being powered by a HMC976 (low noise linear voltage regulator).