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Using Model-based Design for SDR, demodulation process

Question asked by marcinsztajn on Feb 21, 2017
Latest reply on Mar 17, 2017 by ACozma

Hi ACozma dpu

I am trying to understand demodulation process in this tutorial: 

I have problems with understanding some computations. For example:

- in Detector block in stateflow chart, variable T0Delay is used to wait for 25 samples in case SyncCorr will increase above maxSync? Am I right? what is the purpose of this variable?

- in Detector block in Bit Process block, what is the purpose of the HDL Counter and comparing it inputs ? 

- and where is algortihm which is comparing detected preable with pre-definied preable?

I will be very greatful if somebody will clarified be those things.

Thanks in advance