I am trying to understand demodulation process in this tutorial: http://www.analog.com/en/analog-dialogue/articles/using-model-based-design-sdr-2.html
I have problems with understanding some computations. For example:
- in Detector block in stateflow chart, variable T0Delay is used to wait for 25 samples in case SyncCorr will increase above maxSync? Am I right? what is the purpose of this variable?
- in Detector block in Bit Process block, what is the purpose of the HDL Counter and comparing it inputs ?
- and where is algortihm which is comparing detected preable with pre-definied preable?
I will be very greatful if somebody will clarified be those things.
Thanks in advance