I'd like to use FMCDAQ2 (on KUC105, no-OS) with its configuration:
- ADC sampling rate is 1GHz.
- Two independent real input channels.
- Two DDCs: DDC0 and DDC1 are on.
- NCO0 and NCO1 are set to Variable IF mode.
- Outputs data type: complex.
- HB1 FIR of both DDCs is on, so decimation ratio is 2 (in my understand, the data bandwidth after DDC is 500MHz).
The JESD configuration parameters:
- M: 4 since there are two I and two Q channels.
- L: 4 lanes.
- F: 2
So the register values on my software:
Reg 008: 0x03 //select two channels
Reg 200: 0x02 //ddc0 and ddc1 = on, I and Q outputs on
Reg 201: 0x01 //decimate by 2
Reg 300: 0x10 //DDC reset
Reg 300: 0x00 //DDC normal
Reg 310: 0x03 //DDC0 variable IF, 0db gain, decimate by 2
Reg 314: 0x00 //DDC0 FTW low
Reg 315: 0x04 //DDC0 FTW high
Reg 330: 0x03 //DDC1 variable IF, 0db gain, decimate by 2
Reg 334: 0x00 //DDC1 FTW Low
Reg 335: 0x04 //DDC1 FTW High
Reg 561: 0x01 //Two complement
Reg 570: 0x91 //m=4, l=4, f= 2
But I don't known how to get IQ samples on each channel (example on channel 0: how to get IQ from adc_data_0[63:0]).
Could you help me, please:
1. Do I configured correct or not?
2. Do I have to modify HDL core? What core and how to modify?
3. In the FPGA side, how I get IQ data in each channel?
Thanks in advances,
With best regards,