I have generated a project for Vivado using the system_project.tcl script as part of the FPGA JESD204B/DAQ2 project targeting KC705 board. I have not made any changes to projects or source code yet. I am using a "standalone" firmware for Microblaze that is the LWIP example project from Xilinx. This project is compiled and being debugged with Xilinx Vivado 2016.2. The issue I'm seeing is that the LWIP stack is not seeing any packets come in on the "receive queue" (which is the lowest level buffer that the Microblaze firmware accesses). Help is needed as soon as possible.