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AD6676 SYSREF calculation

Question asked by DST_ERA on Feb 20, 2017
Latest reply on Mar 3, 2017 by DST_ERA



I'm playing with synchronization of two AD6676 and I have a problem.


I did a calculation of SYSREF frequency and set it up for design. It seems like I have a delay in data streams between these two ADc - like 2~10 samples so synchronization doesn't work.

Everything (FPGA+both ADc) is feeded from same source ( HMC7044)


Can someone please check my SYSREF calculation before I dig deeper into the design looking for the problem (cables, jesd/ADc setting, sysref mode periodic/one-shot...)?



Fadc = 2949MHz, Fref= 245,76MHz , DEC = 12 (IQ_rate = 245,76MSPS)

lanes = 2, F = 2, K = 32, S = 1, 10/8bit encoding


frame clock FC = Fadc/DEC/S = 245,76MHz (or calculated as lane rate/ (10 x F) )

lane rate = 4915,2Mbps  (chosen as 20x to fit datasheet requirements, can be calculated as FC x F x 10)

LMFC = 7,68MHz = maximal SYSREF value (can be calculated as FC/K or as Fadc/(DEC x K x S) )


I tried 3,84MHz and 960kHz values with similar effect.




With kind regards,