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Problems for intergrating custom modulation IP in hdl

Question asked by a820083502 on Feb 18, 2017
Latest reply on Feb 20, 2017 by CsomI

Hello Everyone,


I am using AD-FMCOMMS4-EBZ(AD9364)board with Xilinx AC706 board and configuring it through No-OS driver. In order to add my own modulation(pi/4 DQPSK) module,I delete util_ad9361_dac_upack which in your design and add my custom modulation IP which has three port(clk,rcos_i and rcos_q),rcos_i and rcos_q stand for IQ data,I’m sure my custom IP can work well.Then,I connect this module to axi_ad9361_v1_0(Pin Maping:clk->clk  ,rcos_i->dac_data_i0, rcos_q->dac_data_q0)

After write_bitstream complete,I export it to SDK(include bitstream) and build a SDK project,When I debug SDK project,I find program was stuck at 187 line and could not exit infinite loop.

So can anyone give me some hints to solve it?



Jinggang Liu