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How do you reduce the effective sampling rate of the DAQ2 noOS project for the KCU105 with analog JESD204B?

Question asked by rbanks on Feb 17, 2017
Latest reply on May 25, 2017 by rejeesh



I am working on a project that utilizes the DAQ2 noOS ad_fmcdaq2_ebz project for the KCU105 with analog JESD204B. I have made several modifications to the base project to include PCIe and cannot update the project to the newly released version which claims to make changes to the sampling rate easier. I've gone through many of the forums for changing the sampling rate but none seem to post a full solution to the issue.


We would like to have an effective sampling rate with the DAC (AD9144) of 256Msps and a sampling rate with the ADC (AD9680) of 512Msps.


The clock generator (AD9523) uses a 125MHz oscillator to generate the clocks for the system. I need to replace this with a 128MHz oscillator to generate the 512MHz clocks.


Looking at page 23 of the AD9144 datasheet ( ) shows that the minimum sampling rate is 420Msps. That being the case, I would like to reduce the tx line rate such that the DAC has an effective sampling rate of 256Msps due to the slow data transfer.


To break things up into smaller pieces, I started by keeping the 125MHz and the DAC sampling rate. I then attempted to reduce the lane rate by making modifications to the JESD204B_GT core and the ad_fmcdaq2_ebz.c file as shown below.



With these settings, I was not able to get anything out of the DAC. I would have expected that changing TX_Out_DIV to 2 from 1 would have reduced the lane rate in half to 500Msps on the FPGA side and that changing the channel 4 divider to 4 from 2 would reduce the lane rate in half to 500Msps on the other side. I will note that I am not clear on the functionality of the gt_link structures.


Any help or insight on this would be greatly appreciated.