I have successfully configured the AD9361 via the SPI interface on the FMCOMMS3 board connected to the KCU105 evaluation board. The AD9361 was placed into the 1RX1TX mode and I have been able to successfully retrieve samples from the AD9361 ADC using the LVDS electrical interface on P1 and processed these signals through the AD9361 HDL-based IP core. We are only using the receive channel and the transmit channel remains unused.
In the process or migrating this AD9361 hardware design to a custom board design I have run across the following information listed in the Analog Devices documentation:
On page 105 of the AD9361 Reference Manual (UG-570), there is the following statement:
The P0_D[11:0] and P1_D[11:0] bus signals are usually actively driven by the BBP or by the AD9361. During any idle periods, the data bus values are ignored by both components. Both ports, however, must have valid logic levels even if they are unused.
Also, on page 9, there is following descriptions for bit D4 and D2 of the SPI Register 0x012—Parallel Port Configuration 3
When clear, the data port uses single-ended CMOS. Set this bit to use LVDS. Full duplex (0x012[D3] clear), DDR (0x012[D5] clear), and dual port mode (0x012[D2] clear) are required.
D2—Single Port Mode
When clear, P0 and P1 ports are both used. When set, only one data port is used.
Since we are not using the Transmit capability, I would like to only use P1 in LVDS mode and turn off P0 and place it into single-ended CMOS mode.
But, based on these descriptions, I don't think I can mix the operational modes (LVDS and CMOS) between P0 and P1. Is that true?
If so, that would means I would have to leave both ports in LVDS mode even though P0 is unused. In that case, is there a recommended way to properly terminate the input signals so it would have "valid logic levels" on these unused pins?
Any feedback would be appreciated.